Table 1 EM78PSAP, EM78PSAM and EM78PSFK Pin Description 37 EM78PS-G I-V Curve Operating at kHz max. EM78PSAP Datasheet PDF Download -, EM78PSAP data sheet. EM78PSAP datasheet, EM78PSAP datasheets and manuals electornic semiconductor part. EM78P, EM78PN, EM78PNAM, EM78PNAP .

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This specification is subject to change without prior notice. A, during sleep mode? One security register to prevent intrusion of OTP memory codes? Two clocks per instruction cycle?

Programmable free running watchdog timer? Crystal input terminal or external clock input pin. RC oscillator input pin. Output terminal for crystal oscillator or external clock input pin. If this pin remains at logic low, the controller will also remain in reset condition.

These can be pulled-high internally by software control. Em78p474sap-g can be pulled -high internally by software control. If this pin remains at logic low, the controller will keep in reset condition. R0 Indirect Addressing Register R0 is not a physically implemented register.

Its major function is to act as an indirect addressing pointer. Writable and readable as any other registers. The contents of the prescaler counter will be cleared only when TCC register is written a value. Depending on the device type, Em78pp447sap-g and hardware stack are bit wide. The structure is depicted in Fig. One program page is words long. Thus, the subroutine entry address can be located anywhere within a page. Any instruction that writes to R2 e. Thus, the computed jump is limited to the first locations of a page.

Such instruction will need one more instruction cycle. Bit 4 T Time-out bit. Bit 3 P Power down bit. Bit 2 Z Zero flag.

Set to “1” if the result of an arithmetic or logic operation is zero. Bit 1 DC Auxiliary carry flag.

EM78PSAP 데이터시트(PDF) – ELAN Microelectronics Corp

Bit 0 C Carry flag 5. See the configuration of the data memory in Fig. Set as TCC overflows; flag cleared by software.

R3F can be cleared by instruction, but cannot be set by instruction. IOCF is the interrupt mask register. Internal data transfer, or instruction operand holding. It cannot be addressed. CONT register is both readable and writable. Bit 3 PAB Prescaler assignment bit. IOCB Register is both readable and writable. The ODE bit can be read and written. The WDTE bit can be read and written. Bit 4 SLPC This bit is set by hardware at the low level trigger of wake-up signal and is cleared by software.


SLPC is used to control the oscillator operation. The oscillator is disabled oscillator is stopped, and the controller enters into SLEEP2 mode on the high-to-low transition and is enabled controller is awakened from SLEEP2 mode on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms1 oscillator start-up timer, OST before the next instruction of the program is executed.

The SLPC bit can be read and written.

Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. The ROC bit can be read and written. Enable the wake-up function. Disable the wake-up function. Individual interrupt is enabled by setting its associated control bit in the IOCF to “1”.

IOCF register is both readable and writable. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off i.

During normal operation or sleep mode, a WDT time-out if enabled will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Without prescaler, the WDT time-out period is approximately 18 ms1 default.

There is input status change wake-up function on Port 6, P74, and P The oscillator starts or is running? The Program Counter R2 is set to all “1”. The Watchdog timer and prescaler are cleared. Upon power on, the upper 2 bits of R4 are cleared. While entering sleep mode, WDT if enabled is cleared but keeps on running. The T and P flags of R3 can be used to determine the source of the reset wake-up. Upon waking, the controller will continue to execute the succeeding address.

The WDT operation to be enabled or disabled should be appropriately controlled by software after waking up. Set Port6 or P74 or P75 Input 2. To avoid reset from occurring when the port6 status changed interrupt enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set above 1: Previous value before reset. Check Table 6 2. A power-on condition, 2. The values of T and P listed in Table 5 below are used to verify the event that triggered the processor to wake up.

Table 6 shows the events that may affect the status of T and P. Previous status before reset This specification is subject to change without prior notice.


When one of the interrupts enabled occurs, the next instruction will be fetched from address H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in R3F. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts.

When an interrupt is generated by the INT instruction enabledthe next instruction will be fetched from address H. Table 7 depicts how these three modes are defined. Table 9 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. A serial resistor may be necessary for AT strip cut crystal or low frequency mode.


Nevertheless, it should be noted that the frequency em78p47sap-g the RC oscillator is influenced by the supply e,78p447sap-g, the values of the resistor Rextthe capacitor Cextand even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the fm78p447sap-g of Rext should not be greater than 1 M ohm.

If they cannot be kept in this range, the frequency is easily affected by noise, This specification is subject to change without prior notice. The smaller the Rext in the RC oscillator, the faster its frequency em78p4477sap-g be. On the contrary, for very low Rext values, for instance, 1 K? Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency.

Measured on DIP packages. For design reference only. The option bits cannot be accessed during normal program execution. Watchdog timer enable bit.

Instruction period option bit. Refer to the section on Instruction Set. Code Security Bit 0: XTAL frequency selection 0: XTAL2 type low frequency, Bit 5 dataxheet Bit4: