Quad 2-line to 1-line Data Selectors/multiplexers. This X24C02 device has been acquired by IC Microsystems Sdn Bhd from Xicor, Inc. The X24C02 is. The LSTTL / MSI SN54 / 74LS is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select. S, 1 •, 16, Vcc. 1I0, 2, 15, E. 1I1, 3, 14, 4I0. 1Y, 4, 13, 4I1. 2I0, 5, 12, 4Y. 2I1, 6, 11, 3I0. 2Y, 7, 10, 3I1. GND, 8, 9, 3Y. Pin, Symbol, Description. 1, S, common data.

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Static page of welcome. In general, the selected entry carries 7457 index the state corresponding to the combination of the entries of order. Let us examine simplest of the multiplexers, that with 2 ways.

Forms maths Geometry Physics 1. How to make a site? The first circuit compares the weak weights of A with the weak weight of B. A multiplexer can be compared with a mechanical switch. Figure 29 represents the diagram symbolic system and the 74175 equivalent of a multiplexer with 4 ways. The number of the inputs of a multiplexer defines the number of ways of a multiplexer.

We deduce the equation from it from S following: For example for a multiplexer with 4 waysone needs 2 entries of order. Return to the synopsis. If a multiplexer has n input, it is said that it is about a multiplexer with n ways.

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### Binary Comparators CI , Multiplexers CI

Form of the perso pages. By putting in series two comparatorsone can 47157 two numbers of 8 bits. Thus, one can compare numbers of 8, 12, 16 bits…. Electronic forum and Infos.

To contact the author. The number of the entries of order is a function of the number of ways of the multiplexer.

According to the state of the entry of selection Athe exit S recopy either the D0 entry, or the D1 entry. Dynamic page of welcome. Figure 25 gives the diagram symbolic system and the mechanical equivalent of a multiplexer to kc ways.

This table, one can extract the equation from the exit S following: The integrated circuit is a comparator 4 bitsi.

Its equation is thus A. A binary comparator is a logical circuit which carries out the comparison between 2 generally oc binary numbers A and B. The integrated circuit is a quadruple multiplexer with 2 ways at entry of common selection. The stitching of this circuit is given on figure 21, while figure 22 represents its logic diagram.

All these considerations are translated in the truth table of figure Electronic forum and Poem. In this chapter, we will examine logical circuits very much used to switch data: The stitching and the logic diagram of this circuit are given on figure We will iic how to produce using logical doors a comparator of 2 binary digits.

## Quad 2-line to 1-line data selectors / multiplexers 74157

That is to say to compare the two binary digits A and B. Using one or several entries of order, one switches one of the inputs towards the exit.

That is translated in the table of figure A multiplexer can thus switch data made up of several bits. The combinative network of figure 26 can provide the signal S.